The invention relates to a digital detector circuit for recovering the bit timing from a data stream, an EFM data stream preferably being considered which is read during the reproduction of a CD. The digital detector circuit is in this case a component part of a phase-locked loop (PLL).
In known systems for recovering the bit timing of a data stream such as is used, for example, in data decoders for optical disks, for example CDs, the clock signal of the phase-locked loop must be locked onto or synchronized with the incoming data signal in the correct phase, so that the bit information of the data stream can be decoded. Thus, in known systems, for example in a CD player, coarse tuning until the PLL is locked on is effected by the regulation of the disk motor. On account of the mechanical inertia of the motor, this operation is relatively slow and susceptible to faults. Furthermore, the phase-locked loop only has a small capture range in conventional solutions.
The invention is therefore based on the object of realizing a bit timing detector which makes it possible to provide a PLL having an improved capture range.